ATMEGA169P-16MCHR【PDF 197/274 页】MCU AVR 16KB FLASH 16MHZ 64-VQFN

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8018P–AVR–08/10

ATmega169P

7.6.2

EEDR – EEPROM Data Register

Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

7.6.3

EECR – EEPROM Control Register

Bits 7..4 – Res: Reserved Bits

These bits are reserved and will always read as zero.

Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-

rupt when EEWE is cleared.

Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.

When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at

the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has

been written to one by software, hardware clears the bit to zero after four clock cycles. See the

description of the EEWE bit for an EEPROM write procedure.

Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address

and data are correctly set up, the EEWE bit must be written to one to write the value into the

EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-

erwise no EEPROM write takes place.

Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct

address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed.

Bit

765

432

0x20 (0x40)

MSB

LSB

EEDR

Read/Write

R/W

Initial Value

Bit

765

0x1F (0x3F)

–

EERIE

EEMWE

EEWE

EERE

EECR

Read/Write

RRRR

R/W

Initial Value

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